How do I assign new bindings and how do I change existing bindings?

Author (required): Al Layson

Platform/Format: VBScript

Use case description (required)

This script will generate a tp_report.txt in the pcb/LogFiles directory of the Expedition pcb design allowing access through Expedition's FileViewer.  It reports the total number of testpoints used, Net Name, Number vs total for net, RefDes, Pad, Layer, X Loc, YLoc, Hole size and Plated state if applicable. At conclusion the script will open the file in WordPad. If not available on your system, change this in the script.

This script reports on all the Diff Pairs defined for a pcb design, reporting the specifications in Expedition for each Diff Pair and its member nets. Does not look at CES data, just the resulting definitions in Expedition. This script was used to help diagnose various problems regarding diff pairs in Expedition. A diff_pairs.txt report is generated to the pcb\LogFiles directory (therefore available to FileViewer) and contain the information shown below for each diff pair: (a -1 indicates no value entered)

(   38) FAST_IO1_DN0,FAST_IO1_DP0

           Delay Tolerance : -1
           Length Tolerance : 5
           Max Convergences Tolerance : -1
           Max Distance To Convergence : -1
           Max Separation Distance : -1

           FAST_IO1_DN0

                 Number of Opens : 0
                 NetClass : FAST_IO
                 NetClass Layers : 1, , 3, , , 6, , 8
                 NetClass Diff Pair Spacing : (Master) 6, 10, 10, 10, 10, 10, 10, 6
                 NetClass Diff Pair Spacing : (Minimum) 5, 10, 10, 10, 10, 10, 10, 5
                 MatchLengthGroup : 5
                 MatchLengthGroup Tolerance : 10
                 MatchLengthGroup Type : 1
                 Delay Formula :
                 Min TOF : -1
                 Max TOF : -1
                 Min Length : -1
                 Max Length : -1
                 Max Number of Vias : -1
                 Number of Traces in Net : 3
                 Total Length of Traces on Layer (8) with width of (6) : 79.09
                 Total Length of Traces on Layer (1) with width of (11) : 27.8388188976378
                 Total Length of Traces on Layer (6) with width of (5) : 3462.44913385827
                 Total Length of Net : 3569.37795275591
                 Total Vias on Net : 2

           FAST_IO1_DP0

                 Number of Opens : 0
                 NetClass : FAST_IO
                 NetClass Layers : 1, , 3, , , 6, , 8
                 NetClass Diff Pair Spacing : (Master) 6, 10, 10, 10, 10, 10, 10, 6
                 NetClass Diff Pair Spacing : (Minimum) 5, 10, 10, 10, 10, 10, 10, 5
                 MatchLengthGroup : 5
                 MatchLengthGroup Tolerance : 10
                 MatchLengthGroup Type : 1
                 Delay Formula :
                 Min TOF : -1
                 Max TOF : -1
                 Min Length : -1
                 Max Length : -1
                 Max Number of Vias : -1
                 Number of Traces in Net : 4
                 Total Length of Traces on Layer (6) with width of (5) : 3462.44913385827
                 Total Length of Traces on Layer (8) with width of (6) : 81.0826377952756
                 Total Length of Traces on Layer (8) with width of (7) : 4.57874015748031E-02
                 Total Length of Traces on Layer (1) with width of (11) : 27.8388188976378
                 Total Length of Net : 3571.41637795276
                 Total Vias on Net : 2

Location of the zip file: http://communities.mentor.com/docs/DOC-1821

Disclaimer

Copyright 2010 Mentor Graphics Corporation. All Rights Reserved. Recipients who obtain this code directly from Mentor Graphics use it solely for internal purposes to serve as example Java or Java Script plugins. This code may not be used in a commercial distribution. Recipients may duplicate the code provided that all notices are fully reproduced with and remain in the code. No part of this code may be modified, reproduced, translated, used, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics, except as expressly authorized above. THE CODE IS MADE AVAILABLE "AS IS" WITHOUT WARRANTY OR SUPPORT OF ANY KIND. MENTOR GRAPHICS OFFERS NO EXPRESS OR IMPLIED WARRANTIES AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTY OF NON-INFRINGEMENT. IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Hi,

I have designed the schematics in dx designer. Now I am generating the cadence allegro compatible netlist but I am having below error.

***********************************************************************************************************************************************

pcb: Note 6057: design sym CONNECTOR:CONN_3N-1: VALUE=CONN,ELEC: Bad property value

pcb: Error 6034: Illegal character

pcb: Error 6079: design sym ICS:PACKETENG_560_8: PINSWAP=(SPARE_8,SPARE_7,SPARE_6,SPARE_5,SPARE_4,SPARE_3,SPARE_2,SPARE_1,SPARE_12,SPARE_11,SPARE_10,SPARE_9): Hetero device property conflict

pcb: Error 6079: design sym ICS:PACKETENG_560_12: PINSWAP=(NC_30,NC_29,NC_28,NC_27,NC_58,NC_26,NC_57,NC_25,NC_56,NC_24,NC_55,NC_23,NC_54,NC_22,NC_53,NC_21,NC_52,NC_20,NC_51,NC_50,NC_19,NC_18,NC_49,NC_17,NC_48,NC_16,NC_47,NC_15,NC_46,NC_14,NC_45,NC_13,NC_44,NC_12,NC_43,NC_11,NC_42,NC_9,NC_10,NC_41,NC_8,NC_40,NC_7,NC_6,NC_5,NC_4,NC_3,NC_2,NC_1,NC_39,NC_38,NC_37,NC_36,NC_35,NC_34,NC_33,NC_32,NC_31): Hetero device property conflict

*******************************************************************************************************************************

I have attached xls and high lighted errors with yellow color.

These are the known error as dx designer help it self provides the solution as given below

========================

PCB-6034

Message:  Illegal character [character]. 

Cause:  The attribute value indicated in the following message contains the illegal character shown. 

Solution:  Fix the attribute value, enable automatic fixups, add a GENVAL fixup, or change the PCB configuration file to allow this character. PCB Configuration File: CHKVAL _NAME_CHK, CHKVAL _LIST_CHK, GENVAL. 

===============================================

But I dont know how to implement the solution in design.

I tried to solve by searching value "CONN,ELEC" in design and yes this is symbol name of connector. So do I need to change the name of symbol ? Because there are lots of instance are there.

Please suggest a better solution.

-

Thanks,

mahesh

Is there a way to get partlister to NOT be case sensetive? It's seems real absurd that Verification is case insensetive, while partlister is case sensitive! We turned on lower case for ITAR & EAR classifications (which MUST be mixed case), now we find out partlister seperates items with mixed case from items with upper case.

I have resisted for years making the switch, there was just too much Logic legacy here.  I didn't want to maintain 2 libraries and design flows.  The VX release changed the xDx library structure, we purchased HyperLynx, so now seemed to be the time.

I'm running into a LOT of questions.  Getting quite frustrated.

What I've found is the library migration is not really so straightforward.  There are enough differences that need to be addressed first.  Simple things like Logic uses "\" prefix to negate a symbol, xDx uses "~" (prefix or suffix, I'm not sure since i can't figure out how to show pin names)

What I think I'm realizing is that the new xDx library structure is NOT the same as the PADS Flow (Logic or Layout).  In PADS Flow, the Part Type gathered up a generic logic symbol and PCB decal, assigned pin numbers and names to both, and used the same Part Type on the schematic and board.  xDx seems to be more like Board Station, where the logic symbol is not generic, it must have pin names and numbers already assigned.  the Part Type is only used to connect the symbol to a PCB decal, using a packager.

This is a HUGE difference in the way libraries are managed!  I'm having second thoughts about changing to xDx.  Has anyone else been able to do this successfully?  I'd like to share ideas, maybe we can all figure this out together?

What I've done and found so far:

If a (Logic) CAE decal is used in a part type that has pin names assigned, the library migrator creates a new symbol.  For example, I have quite a few op amps, all using a single CAE decal and "+" and "-" pin names assigned in the part type.  xDx creates quite a few op amp symbols, all exactly the same.   If I remove the pin names, it lets me use the same symbol for all my op amps.  I removed as many pins names as possible from my Part Types prior to conversion, I'll have to live with the rest of the additional symbols created.  But this makes library management much harder.

The aforementioned "\" vs "~".  Again, edit the entire library to change all of these.  That's as soon as I can figure out is the "~" goes before or after.

CAE Decals allowed pace holders for any attributes you wanted to display, called "Free Label".  The library migrator doesn't handle this, you must go back and explicitly assign the desired attribute display.

xDx will not allow gate swapping using different symbols, as Logic did.  For example, I had created inverted symbols for many gates so that I did not need to clean up text when i wanted to rotate a gate. The migrator strips the swap code in these cases.  For safety's sake, I had to remove all of the alternate decals to preserve swap codes.

the PINB inverted pin becomes just lines in xDx.  Manually making this an inverted pin creates a "double bubble" pin.

With almost 4000 Parts in my library, I ended up exporting to a text file so i could write Visual Basic in Excel to clean all this up pre migration.  I don;t have an idea on automating the post migration cleanup requirements.

Any body else doing this?  It's not helping that I have no training in xDx, and my company will not pay for any.  I'm sort of flying blnd here.

Pete

HI,

I'm currently making some small modifications to already existing PCB layout in Pads Layout 9.4 (I'm editing it with Pads Layout 9.5).

I suppose that I have a ES edition.

For some specific reasons I have to route my differential pairs out of the connector between two pads (pad gap diff_trace+ gap diff_trace- gap pad).

Normally my width and gap for diff pair is bigger, however when routing out from the connector I have to make the traces and gap smaller to do it (I can live with

impedance mismatch - rs422 diff pair).

I can't solve how to do it, there are some settings to make different width/gap for different layers (of course to account for controlled diff pair impedace).

However I would like to do it on the same layer.

Do you have any suggestions ?

Best,

Pawel

Hello,

I generate the SVDB database for a design using Calibre nmLVS, and next step I need to generate the CCI database based on the SVDB. Basically I used the script below to generate the CCI data:

calibre -cb -nowait -query ./svdb TopCellName < CCI-SCRIPT.txt > query.log

TopCellName is the top cell name of the design in the source/layout. Here I used the CCI-SCRIPT.txt file to control Calibre during generation. In this file there are three commands that I am not sure what they mean and what the number stand for. Could anyone provide me more information? Will really appreciate that!

#specifies GDS property values for attributes, corresponding to nets, instances and devices

  gds  netprop number 5

  gds  placeprop number 6

  gds  devprop number 7

Thanks!

Please help.

Is there any straightforward way of somehow converting or translating or import/export between PADS Professional and Xpedition VX.1 in terms of schematic, library and the pcb (vice versa)?

Issue of the day:  Adding fiducials.  I have a round pad with a round opeing in the plane around the pad.  I used Plane Area Cutout to make the opening.  I decided to move the fiducials to a better area, now the Plane Area opening is stuck in the old location.  Tried to delete all the plane data and re-do it, but it is still there.  Any suggestions??

Thanks,

Bruce

I am currently working on a board design that started out one size of Board Outline, then got changed to a second a different size. On the design screen I see the second - and, correct - board outline. However, when I go into 'Create PDF' I see both the old and new Board Outlines. Just in case this was an image artifact I went into CAM and created some artwork. The 'old' board outline also appears there.

Can someone point me in the direction I need to go to remove all remnants of the 'old' Board Outline ?

Thanks,

Mr. Amalfi

When using a plane/copper-pour layer is it necessary to physically route the connections attached to that plane ?  I.e., I am using a copper pour layer connected to the net 'GND'. I have many components which are connected to the 'GND' net. I routed some of these GND connections, however, when I go into 'Verify Design', I am getting many (para-phrased) 'Error, Subnet of net 'GND' I feel this may be due to the fact of these individually routed 'GND' net connections.

Is this similar to the case when stitching vias, i.e., they don't actually get routed, they are just connected between the plane layers ?

Can someone please clarify ?

Thanks.

I need to "shoehorn" in a few components in the PCB layout.  I spent a lot of time actual routing the design and would like to save as much as possible.

So I selected the components on the PCB that I had already placed and routed to/from and tried to move them over, but got an Expedition PCB pop-up

error message that popped up saying "A large number of traced need to be shoved, it may be faster to rip them all up before routing.  Do you

want them ripped up?".  I then hit "Yes", but that message keeps on popping up again and again and I can't land the components that I want to move

where I want them to be.

I use a USB hardware dongle. Occasionally, during program use, I get an error saying that my key isn't detected. Sometimes when this happens I just clear the error and keep going. But sometimes the program exits abruptly. So a couple of times I've lost changes.

This has been happening for a long time, maybe ever since I've been using the software (over 4 years). It may be happening more often, not sure, but I would sure like to know if this is a known issue and if there is a solution for it. Thanks in advance.

I am currently working on a board design that started out one size of Board Outline, then got changed to a second a different size. On the design screen I see the second - and, correct - board outline. However, when I go into 'Create PDF' I see both the old and new Board Outlines. Just in case this was an image artifact I went into CAM and created some artwork. The 'old' board outline also appears there.

 

Can someone point me in the direction I need to go to remove all remnants of the 'old' Board Outline ?

It is not possible for PADS to have 2 Board outlines, but what can happen, is import of a new outline is flipped over to 2D polyline (usually with a message.)

If you want to use a newly created/imported  2D closed polyline as a Board outline, you need to first select shape on the old board outline, delete, then select shape on the 2D polyline and change it to a Board Outline. This new outline is then used for clearance checking, zoom etc.

So I have finally got my wonderful 2014 updates installed to play around with and have decided to step into the world of report builder something I was highly anticipating.

So the interface is interesting takes a little getting used to has alot of things there.  probably 80 precent of it I have no idea what it is or where its used.  I talked about this kinda thing when we first got vesys nearly two years ago that there was a need for it.   I do have a question though of what kinda of customer testing and feedback occured because I have questions.

First of all we pay alot of money for support for and access to updates.   When you do a search for report builder in the help menu you recieve a very limited heres the button you press drag and drop and you wash your hands of it.   A 15 min video would go a long way.

A proper break down of each category in a pdf document would be nice. With at least a description of which each major field entails PRetty much its a hunt and peck procedure to find what you want.   You don't even have a picture or explain the connector and wire components splices ect options you enable and disable to bring into the chart.

Again i mentioned the 80 percent of things that i have never heard of or used.  But you know what i use every day.   What page number does that wire or connector appear on.   What zone location on the page.   Attributes already used in the default wire table chart.   Terminal information  is also missing in the harness section.  Multicore identifiers. 

You have the option for user specified attributes.. How do i use these?  Will this solve my problem if i know the right code to type in?

{diagram.index} was my page number i used on the borders this doesn't work in these specified fields.

Again i'm glad you guys made the effort but all i really needed was some basic stuff.  So let me know what i can do.

Hi,

I am exporting CCZ file for my PCB layout.

In the message window, the following message is displayed:

"Info: CCZ exported with errors, please refer to CCZExportLog.txt for more details."

Bu there is no file in the specified location. Also, after this I am not able to close the design.

Whenever I click on close button then it asks for saving of the data. But It did not close it.

Please let me know if anyone has ever faced this issue. If yes then please let me know how to resolve this issue.

Thanks & Regards,

Sunny Watts

Tel: +91-9999907724

Email ID: sunny.watts@keysight.com

Skype: sunny.watts

Hi,

How can I model X2Y capacitors in HyperLynx PI (Boardsim)?

Regards,

Charl

Hi,

I would like to deep in understanding VIA properties in Hyperlynx. In theory, do you know how Hyperlynx calculates VIA properties such as odd mode impedance (Zodd), individual via impedance (Zvia), the effective dielectric constant (Dkeff) based on its geometry, capacitance for Cvia. ?

Thanks and kind regards,

Nguyen

I encountered issue with diode symbols in ODA starter library. When I tried to create new part (zener diode) I used Part Editor, assign a PCB Decal, Gate (DIODE-ZENER) and set up pins as requested and check the part. According to Part Editor it has no errors or warnings.

But when I click OK, create a part it has no Associated Symbols. When I add normal diode symbol to Gates it shows it in the xDM Library Tools but no other diode symbol (as shotky or any TVS diode) included in the ODA libraries is associated with the part. Even when I add almost all symbols from Diode library as alternative symbols only normal diode symbol is displayed in xDM Library Tools as Associated Symbols.

And furthermore if I open any existing diode with Associated symbol of zener, schotky or any other than normal diode in Part Editor and click OK, xDM Library Tools shows no Associated Symbols although it is associated in Part Editor. I am able to create for example resistor part without any problems.

Do you have any idea what can cause this issue? Where am I making mistake in the process?

Thank you for any advice.

Radek

P.S. Library can be fixed in PADS version VX.1, where associating symbols works correctly.

Microsoft announced Windows 10 definitely in the summer, but possibly late July 2015.

Windows 7 and 8.1 PCs will get direct upgrade to Windows 10.

Are all Mentor tools at that time ready for Windows 10?

What is Mentors road path to Windows 10?