Helo,
As am working in schematic style set alteration I want to show total number pins in a connector. And it should called from vesys component library. I have tried this option to show number of pins in a connector, but I got only the option "number of pins in use". If anybody having idea how to show the total number of pins in a connector, let me know.
Thanks and Regards,
Manoj
+91 8973234943
Hi,
As per vesys classic input we would like to show node to node dimension, We don't want to show major dimension, we want to show only point to point distance information. I tried to control this through style set but, if I hide this major dimension in style set, dimension in bundle without node are not visible
Image for your reference,
After Hiding Major dimension through style set, Dimension are not visible,
Let me have any suggestion to show point to point dimension...
And is there any option to show dual dimension as like vesys classic,
Regards,
Manoj
Hi all ,
I am working with Tie legs, ther is no problem to change and modify it , but sometimes i need to reset or "Remove thermal Override" and i can't do it .
Useless --> UsePadstackThermalDefaults - in my case i set it False and True and it's gave me same result in "Pin Thermal" Properties and sets "Default through hole connections" even "Use thermal definition from padstack" are marked .
1.As you can see no Override .
2.UsePadstackThermalDefaults Set True
3.UsePadstackThermalDefaults Set False and it's same as True .
I saw lot of discussions about but without answers , in my opinion it's Mentor BUG .
if you know some workaround please share it here .
Thanks you .
I'm astonished to see SPac 1 released without major Bugfixes.
Is EE 7.9.2 really running stable, or is nobody using it up to now?
What are you experiences on EE 7.9.2?
Any new issues found, compared to EE 7.9.1?
Any feedback is appreciated.
Best regards
Dirk
Hello all,
I had a harness designed with diodes integrated in the harness bundle. I am not sure of option to tape the diode individually inside the conduit(tube)? is that any way I can do it in Vesys?
Many Thanks
Best Regards
Andrew
It would be good to grey out the selection for 'integrated projects' when a user has a 'PADS Standard' Suite license. For new users this will save confusion. There is a license warning message but it not self explanatory. "There is no PADS license feature available. Project will not be opened."
Maybe if it read "integrated projects are not supported with your current license".
Just a suggestion.
My ruler tool behavior has changed, started getting curvy on me and measuring from origin instead of the first point I click. How do I modify this? I want straight point-to-point measurements.
Hello again! I made a block with 4 pins: VDD, GND, in, out
When I run nmPEX and I read the netlist, I see it finds capacitances between GND and net0! What is net0? How should I have to interpret it? Let's say I have a capacitance between out and GND, and another one between out and net0: should I have to add those capacitance (thus considering net0=GND)? What about the capacitance between GND and net0, then?
Thanks for your help!
this is just an admin test.
I’ve got a 2 conductor cable I would to apply heat shrink to the insulation cut back on both ends, what is the best way to show this and get the heat shrink to show on the BOM?
This document explains all the factors and data point considered by the Tuning Meter, and discusses how it arrives at the ranges and targets shown and why they can differ from the ranges shown in Constraint Manager. It covers how to interpret the Tuning Meter and use it as a helpful interactive guide to tuning routing within tolerance within the layout tool alone.
https://supportnet.mentor.com/portal?do=reference.technote&id=MG591953
Hello everyone,
Is there any way to import HKP files to PADS VX? My issue is that neither Accelerated Designs ' Ultra Librarian or PCB Libraries' Library Expert support importing to the PADS VX Integrated Flow. Both applications do support exporting to Expedition via HKP files.
And Yes, I already did check PartQuest... None of the parts I need have footprints there.
Hello,
Is there any option to customise DRC(Design Rule Check) option in vesys 2.0 as our customer wants the limited reports.
Regards,
Manoj
I'm running into a problem with cDC I/O Designer VX.1, where it will not update the FPGA libraries via the Internet.
The following error dialog box comes up when I try to run the update:
"Could not load data from manifest file: C:
\Uses\<MYUSERNAME>\iod_updates\update.xml
Updater will be closed. You can read details in the log file:
C:\Users\<MYUSERNAME>\iod_updates\log\2015-09-30-11-28-09.log
The text of the log file is:
Current version of xDX I/O Designer IOD9.7
Current version of library 097_000_000_000
Using server http://supportnet.mentor.com/productupdates/
Downloading manifest file http://supportnet.mentor.com/productupdates/public/iod/libraries/IOD9.7/update.xml
Warning: Could not download manifest file : http://supportnet.mentor.com/productupdates/public/iod/libraries/IOD9.7/update.xml
Warning: Connection refused
Error: Could not connect with server to download manifest file.Connection refused
Update: I solved the first issue. Now I get this log file
Current version of xDX I/O Designer IOD9.7
Current version of library 097_000_000_000
Using server http://supportnet.mentor.com/productupdates/
Downloading manifest file http://supportnet.mentor.com/productupdates/public/iod/libraries/IOD9.7/update.xml
Manifest file : http://supportnet.mentor.com/productupdates/public/iod/libraries/IOD9.7/update.xml was downloaded successfully to path C:\Users\admin-dittrich\iod_updates\update.xml
Loading manifest file C:\Users\admin-dittrich\iod_updates\update.xml
Error: Could not load data from manifest file : C:\Users\<MYUSERNAME>\iod_updates\update.xml
And the file C:\Users\<MYUSERNAME>\iod_updates\update.xml is:
<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html><head>
<title>302 Found</title>
</head><body>
<h1>Found</h1>
<p>The document has moved <a href="https://supportnet.mentor.com/productupdates/public/iod/libraries/IOD9.7/update.xml">here</a>.</p>
<hr>
<address>Apache/2.2.29 (Amazon) Server at supportnet.mentor.com Port 80</address>
</body></html>
Anyone have any ideas?
Best regards, Michael
I'm trying to export a DXF drawing of my assembly outlines and reference designators. For the top side this works fine. On the bottom side all reference designators have an offset. They are starting at the position where they should end.
At first it seems he is trying to mirror the text on a Edge.
But now I tryed all combinations of different text origins, text mirror checkbox & export mirror checkbox enableing and the result is allways the same.
There must be another option.
Is there an alternative to export am assembly drawing?
I'm using X-ENTP VX.1 Update 14
Regards, Michael
I've been trying to output true type font from the silkscreen generator with no success. All the silkscreen generator does is outline the true type font. I come from a PADS background and have used true type font on many designs with no issues, is it possible to use true type fonts on the silkscreen in Xpedition VX 1.1? If so, how?
to whom it may concern,
I requested for a free PADS viewer SW yesterday, and, after receiving and installing the viewer through an auto-generated activation email, the display language of the viewer turned out to be in simplified Chinese (note: i live in Taiwan and the common written language here is TRADITIONAL CHINESE). To my dismay there’s no way to change the display language and all the menu items are gibberish to me. Can you pls supply me with an ENGLISH viewer? Thank you so much!
Howard Chang
Hallo eveybody,
I'm trying to run Floefd 14.2 on creo 3.0 M050 but i get always this error:
"unable to run EFD.pro Toolkit5 Utils"
When I load an assembly Flow analysis tab appears but There isn't the FloEFD project TREE !!!!!!!!
Anyone has any IDEA ???????
Regards
Greetings
We had create the generic symbol without pin number in DxDesigner and manually mapping it with physical pin.
Can anyone suggest is there any script for part mapping if the symbol is created without pin number.
We are using Expedition EE7.9.3 version.
Thanks in advance
Mani