Hello,
I'm trying to use Pyxis OpenAccess Importer/Exporter to import Global Foundry OpenAccess 0.13 BCDlite kit. Following the instruction in import/export process in Pyxis Project Manager manual. I have imported the kit, however, all layouts has been imported as fixed cells, not PCells. What is the reason for that?
Thanks,
Rana
Related to a previous mouse cursor (in DxD / xDX) location question, I want to pop up a form right where the mouse is. What sets where the form pops up? Right now, the form is popping up on another monitor entirely.
Looks like there is no active document command in VB .NET for drawing editor application.
Could you please check and let us know if there is any alternate solution for this ASAP?
Appreciate any quick response on this.
Hello All,
This is to request you to suggest the method that can be adopted to read only composite symbols directly from Dx-Designer, instead of scanning through all the symbols in all the schematic sheets.
Any ideas or methods used in the past are much appreciated.
Thanks & Regards,
Bharadwaj.C.V.S
I don't seem to have the ability to download ModelSim SE 10.2c and/or 10.3 from SupportNet. Where can I download the software to which I'm licensed to run?
Thanks,
Dave
1. The HyperLynx Analog Simulation often throw out some strange error information.
2. The way that the xDX Designer introduce the error information is very bad. For example, there is not any special color or mark when the error information comes out. People must look carefully for the introduction information in a very long graph. People want get some hint just with one simple clicking on the screen to get the part or net.
3. It is very difficult to add some Probe point on the drawing. Absolutely, it will be better that to add probe point in the same way as the Pspice in orcad.
4. As the two files in attach, the HLA_DJD.ZIP will make the HyperLynx Analog Simulation throw some error information shown below:
include "resultDisplayFile.Aqr"
.include "..\..\genhdl\Schematic1\Schematic1.spi"
..\..\sym\s__zener_hv.spi(2): error -- s__zener_hv is a duplicate subcircuit element.
..\..\sym\s__zener_hv.spi(3): error -- VZ is a duplicate parameter.
..\..\sym\s__zener_hv.spi(4): error -- IR is a duplicate parameter.
..\..\sym\s__zener_hv.spi(5): error -- VR is a duplicate parameter.
..\..\sym\s__zener_hv.spi(6): error -- TCVZ is a duplicate parameter.
..\..\sym\s__zener_hv.spi(7): error -- IZK is a duplicate parameter.
..\..\sym\s__zener_hv.spi(8): error -- ZZK is a duplicate parameter.
..\..\sym\s__zener_hv.spi(9): error -- IZT is a duplicate parameter.
..\..\sym\s__zener_hv.spi(10): error -- ZZT is a duplicate parameter.
..\..\sym\s__zener_hv.spi(11): error -- CZ is a duplicate parameter.
..\..\sym\s__zener_hv.spi(15): error -- the name vt appears twice in subckt .
..\..\sym\s__zener_hv.spi(16): error -- the name isd appears twice in subckt .
..\..\sym\s__zener_hv.spi(17): error -- the name r2 appears twice in subckt .
..\..\sym\s__zener_hv.spi(18): error -- the name nz appears twice in subckt .
..\..\sym\s__zener_hv.spi(19): error -- the name tcr1 appears twice in subckt .
..\..\sym\s__zener_hv.spi(20): error -- the name r1 appears twice in subckt .
..\..\sym\s__zener_hv.spi(21): error -- the name rz appears twice in subckt .
..\..\sym\s__zener_hv.spi(22): error -- the name v1 appears twice in subckt .
..\..\sym\s__zener_hv.spi(23): error -- D2 is a duplicate diode element .
..\..\sym\s__zener_hv.spi(24): error -- D3 is a duplicate diode element .
..\..\sym\s__zener_hv.spi(25): error -- R1 is a duplicate resistor element.
..\..\sym\s__zener_hv.spi(26): error -- E1 is a duplicate voltage-controlled voltage source element.
..\..\sym\s__zener_hv.spi(28): error -- I1 is a duplicate independent current source element.
..\..\sym\s__zener_hv.spi(29): error -- R2 is a duplicate resistor element.
..\..\sym\s__zener_hv.spi(30): error -- dm is a duplicate model.
..\..\sym\s__zener_hv.spi(36): error -- dl is a duplicate model.
.option tnom=27
.option dcmode=all gmin=1e-12 nodeset=1
.option trmode=fast
.option method=trap
******end of additional commands*******
.end
After the "D2" was deleted, the error information is disappearing. But as you know, D2 and D5 are all come from the library located in the director which path is \SDD_HOME\standard\templates\hyperlynx analog\Central Library\HLASym_CentralLibrary .
If the D5 is deleted, the error information is also disappearing, but new error information such as "no convergence in transient analysis" will shown out, just as the HLA_DJD_2.ZIP.
The error information from HLA_DJD_2.ZIP is shown below:
n1n797 last converged value = 0.904141 new value = 0.91401
out- last converged value = 1.11178 new value = 1.14664
no convergence in xd1.
C:\MentorGraphics\EEVX.1.2\SDD_HOME\dxsim\win64\bin\vbase.exe: error -- no convergence in transient analysis at time 0.400034.
If the R7 is changed to 1M, it's ok!
Other，Sometimespause a few minutes in places shown below.
I want to know what make these thing happen and how to avoid them. It is very difficult to use the HyperLynx Analog Simulation. So many time are wasted on killing these strange thing .
Thank you!
Hi
i created a new project but when i try to package it in give me that ERROR:
ERROR: The Common DataBase cannot be locked for writing:
Object already locked (While trying to lock object)
!THE iCDB WILL NOT BE UPDATED!
can someone help me with that
HI All,
is there any easy way to convert imperail PDBs (Symbols and Cells with inch grid) to metric?
Background: for e.g. CPUs I get the PDB often from the vendor, unfortunately in inch, as our complete library use metric I have to create the whole PDB by myself with metric grid. I'm not able to use the vendor data. I talk about parts with a lot more than 1000 pins.
Regards Tobi
Hi all,
I need to base my design on a foreign design. I have the foreign project and the foreign library.
Obviously all parts in this design are not known by our companys library nor by our production system.
Whats the best way to manage this?
So far I see two options:
Option A: integrate all parts from the foreign design in our libray AND integrate all parts in our production system AND buy all these parts
Option B: exchange parts by already known ones, how to do this fast and partly automatic
Does anybody have experience with such kind of job?
Kind regards Tobi
I do an Edit->Copy to Layout Clipboard of some parts and traces on my board. I then do an Edit -> Paste from Layout Clipboard. The silkscreen outline for the components does not then get pasted, the traces and component pads and placement outlines do. If someone would offer a suggestion on what might be the problem I would greatly appreciate it.
Ken
I've installed a new floating license file 3 times on our shared server
Users are still getting a message that the license will expire in 30 days.
When I looked on the users computer I see this
I'm assuming the local copies of the license are bad, but I could be wrong
The bottom line is correct that is the floating server license.
Is there are way to remove the two local copies, maybe going to the location and deleting the files? Are these local copies causing the issue?
But are logged into PartQuest. Log out of the PartQuest website and log in again. This should reset the connection.
Eventually, I haven't found HISR or TASK from Soucery Analyzer because these are seen as a unknown.
Is there anybody who know why it's happening and how to resolve this?
Good day,
I received a question from my customer regarding Integrator's behavior. We understand how the system behave, but we want to know why? and we want to make sure our understanding is correct.
This is the situation;
#4 step will not run CWS after sharing the two nets. In case #1, Integrator will merge the two nets after sharing but all wires will remains. In case #2, Integrator will merge the two nets after sharing and also delete the other wires.
This is what we want to know, why the Integrator system behave this way? Is this what the system will behave? and why?
NOTE:
We understand that at this point the wire are not correct and need to run CWS to have a correct wire. And both case will have the same number of wires after running CWS.
Thank you,
Larry
Hi,
When I tried to simulate my design in Pyxis using Eldo/EZwave, I get the following error.
"wdb file not created"
Any suggestions..??
Regards,
Ram
We have completed a Design (Schematic and PCB) and now have a second design.
The schematics have been completed for the second design, but now I want to use the existing PCB from the 1st Design and forward annotate the changes.
How do I achieve this?
The 2 designs are about 90% similar, with the second design having fewer components on it. Board shape and critical component positions are the same between designs.
Using Expedition VX1.1 with DxDesigner.
Packager fails with the error "The required symbol is not in the Parts Database" when trying to package a recent translated (DC2DX) schematic. The project packaged with just 4 warnings in DC before it was translated. Nothing was changed about the library and no parts were moved to new partitions. All the answers I seem to find is that each part needs to be replaced in order to update the PDB. This project is 2000+ components so I would like to avoid that if possible. Thank you in advance.
Has anyone an idea on how to fix the following problem, we have created a part in our library and exported it to a hkp file.
We have then sent this file to our mirror site (in china) for them to import into there copy of the library.
(for adding a few parts or cells this (used to be) a better way than keep sending complete libraries).
Now when they try to import parts (or cells) they get errors where usually it says unknown keyword - attached is file for latest parts showing error.
This method used to work find in 7.9.1 version of the software - but seems to now be a problem when we are all using VX 1.1 (Expedition Flow)
Because the hkp files are encrypted I cannot double check to see if the keyword in present or not.
Any ideas on how to fix this or what to check etc.
Thanks
Hi Guys,
I'm trying to iterate through component via .NET, but it does not work.
By using "COM Interop" , I got file named "Interop.ViewDraw.dll" .
But the code segment below could not work at all:
ViewDraw.ApplicationDxAppHandle = (ViewDraw.Application)System.Runtime.InteropServices.Marshal.GetActiveObject("ViewDraw.Application");
ViewDraw.IVdSchematicSheetDocumentstempSSD = DxAppHandle.SchematicSheetDocuments(); // tempSSD has counter, butCANNOTiterate through
ViewDraw.IVdObjsDesignObjects = DxAppHandle.Query(ViewDraw.VdObjectTypeMask.VDM_COMP, ViewDraw.VdAllOrSelected.VD_ALL); // CANNOTagain
This problem has troubled me a few weeks, how can I fix it?
Any hints are welcome!
It seems that Mentor Graphics have lost the last change to get back in Signal Integrity and Power Integrity for ever while Ansys, Cadene, Keysight are renewing thier stuff. I don't know what exactly Mentor team think about Hyperlynx. However, I think following items Mentor Graphics may take
1) Mergere Hypelrynx and Hyperlynx DRC A new GUI and API framework is a must.
2) Add Flo.pcb into Hyperlynx. Ansys Siwave now have icepack solver in Siwave.
3) refine Nimbic(accuracyand speed) technologies and the interface for ECAD data
4) Accqures Simbeor to provide a fast GHZ channel synthesis solution.
5) refine integration between XpeditonPCB and Hyperlynx .
yanfeng