Hi,
I am working on a layout and am encountering a strange problem with extraction. I have passed LVS checks in LVS and PEX. My PEX run finishes without errors or warnings, but within the calibre view schematic,the transistors are floating. I am not sure if this is a problem related to the the PDK (TSMC) or if I have some setting incorrect.
I am hoping someone might have a solution to this problem.
Thanks!
nds123
Option Explicit
Dim pcbApp
Set pcbApp = GetObject(,"MGCPCB.ExpeditionPCBApplication")
Dim pcbDoc
Set pcbDoc = pcbApp.ActiveDocument
If (ValidateServer(pcbDoc) = 1) Then
Call Scripting.AttachEvents(pcbDoc, "pcbDoc")
Scripting.DontExit = True
End if
Sub pcbDoc_OnSelectionChange(enumSelectionType)
Dim colComps, oComp, i, myArray()
Set colComps = pcbDoc.Components(epcbSelectAll)
ReDim myArray(colComps.count-1)
For i=1 to colComps.count
myArray(i-1) = colComps.item(i).partnumber
'msgbox myArray(i-1)
Dim colPins, oPin
Set colPins = pcbDoc.Pins(1)
If colPins.count = 1 Then
If myArray(i-1) = "1203-007904" Then
MsgBox " 1. Connect the VOS line(14 Pin) in the shortest way to VOUT line(14 Pin) at the output capacitor" & vbcrlf & vbcrlf & _
"2. To avoid noise coupling into the VOS line(14 Pin), this connection should be separated from the VOUT power line/plane" & vbcrlf & vbcrlf & _
"3. Sensitive nodes like FB Line(5 pin) should be connected with short wires(Pland "
End If
End If
Next
End Sub
Private Function ValidateServer(doc)
Dim key, licenseServer, licenseToken
key = doc.Validate(0)
Set licenseServer = CreateObject("MGCPCBAutomationLicensing.Application")
licenseToken = licenseServer.GetToken(key)
Set licenseServer = nothing
On Error Resume Next
Err.Clear
doc.Validate(licenseToken)
If Err Then
ValidateServer = 0
Else
ValidateServer = 1
End If
End Function
I have a new question. In DxDesigner, is the size of the junction dot adjustable? If so, how?
Thank you.
Rick
I've tried many different custom reports configurations in VeSys and I can't seem to extract the information that is required. I'm able to create a table in my harness design that gives me the information I want, but I am unable to create a report. At the very least I would like to add the customer part number to the standard BOM report? Does anyone know how to accomplish what I'm trying to do?
Table:
If you ever wondered how to make cell pins moveable in a PCB design than this TechNote is for you:
If you ever wanted to start over and delete all the traces and vias in a design than take a look at this TechNote:
If you are unable to Create Config sub-directory in Central Library than this TechNote is for you:
If you ever wondered how to add rules in quickly into the Constraint Manager than this TechNote is for you:
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It is tough to plow traces for Intel chips (SANDYBRIDGE) , it need layout tool to support arc snake plow. How to do arc snake in Expeditionpcb?. Currently, Cadence Allegro have a special command(16.3 from 2010.8) to support this type of plow, it seems that Cadence have a hard-code special plow to this type of plow. the arc snake plow see the attached picture
Yanfeng
Hello ,
Will there be any soldering issues if copper is provided on the QFN thermal pad in all the layers that is outer as well as inner layers ?
Best Regards ,
Parth Sutariya
Hardware CAD Engineer
MATRIX COMSEC
Vadodara , Gujarat
INDIA
If you are unable to Create Config sub-directory in Central Library than take a look at this TechNote:
When people think of the King of Rock and Roll, electronics are likely not among the first things that come to mind. In the latest PADS blog, John McMillan discusses the fascinating role Elvis played in the history of the electric watch. Read it on PADS.com!
Hello,
print preview shows correct dimension, but after printing (Free-PDF or directly to printer) i get this.
Any ideas?
Good morning,
Can Expedition 7.9.5 facilitate multi-layer rigid-flex layout, specifically preventing gerber output for connector pads on middle layers?
Burying SMD pads works great but through-hole pads don't provide the option.
Thank you,
-Brian
Hello,
I am having trouble getting the correct individual conductor lengths within a multicore. I have an MC where 2 conductors are cut shorter than the rest and although my bundles reflect this difference in length, the calculated modified/unmodified lengths do not.
I have attached a picture of the assembly I am drawing as well as a snapshot of my drawing.
Thanks!
Hello all,
If I created a ground network that was created by combining a bunch of ground signals by a common property, can the subsequent wires be routed through a junction slot "automatically" when synthesis is performed?
I've been unsuccessful in my attempts.
I created a junction slot for my ground network, and assigned the following constraint "Only route signals with attribute/property matching Group = “group” here”.
Is what I am asking even possible?
Thank you.
Calibre RVE is opening a new layout window for every highlight. The Calibre DRC job was submitted through Calibre Interactive so the socket is open and the context is correct. This is new behavior and somewhat intermittent. I am seeing it when using a specific TSMC design kit so I am suspicious of that. Just wanted to see if anyone has had a similar experience and how it might be fixed.
Thanks,
Larry Schramm
SR. Staff IC Layout CAD
Microsemi
In xDX Designer, how do I change the grid spacing for text comments? I want this grid spacing to be different than the spacing for other objects such as nets and components. Thanks!
Hi,
does anybody know whether the Navigator in DxDesigner has an API
and which dll to source then ?
Kind regards,
Andreas