If you are going & would like to meet the PADS management team, at a post Exhibition, informal cocktail reception on Wednesday evening, let me know & I'll send you an invite.
Steve Hughes
PADS Product Manager
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Who's attending to PCB West later this month?
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DxDesigner - Displaying "name" property in mutiple places
In my schematic, I have some long nets and I've enabled the checkbox to display the name somewhere along the net. However, to make it easier to read, I really need to display the net name on both ends of the net. Is there a way to do this in DxDesigner? If not, I may have to resort to simply placing text there, which is not ideal.
Thanks for any feedback.
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Library management in Xdx Designer.
Hi Team ,
I am new to this tool . facing some issues with library management xdx Databook.
want to edit with partition , parts,symbols, with some new attributes . how i have to edit ?
Please check the attached document.
Thanks in Advance.
Chinmayee
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What can I do with xPCB Basic Automation?
Hi all,
I have only the license for VX.1.1 xDx and xPCB and so xPCB Basic Automation.
No license for the Library Manager.
I found some Library scripts on the communities, but they are not working.
Sometimes I get the error "Cannot acquire a Library Manager license" and/or "Cannot acquire Automation Pro license"
This is correct because I don't have these licenses.
My question is: what can I do with the xPCB Basic Automation?
Is there a document which explains the differences for Basic and Pro?
Which statements can I use in Basic Automation?
Thanks.
Wim.
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Project is not available
I tried to import a project and everything seemed to work fine. When I went to open the project I can not find it anywhere. However if I try and import it again it shows that the project already exists.
Now when I try and update components it shows this project is using some components so I am unable to edit them.
How do I delete this project if I an unable to locate it?
Thanks
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Vbsedit object browser does not show Mentor objects in VX1.1
Is anyone using Vbsedit to edit scripts in VX1? I've found that the Mentor objects are not displayed in the object browser they way they are in version 7.9.5. Does anyone know how to fix this?
Thanks,
Kelli Hosier
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Where can I report a QuestaSim bug?
I'm new to this community. I would like to report a bug in QuestaSim. Where and how can I do this?
My testbench (< 1000 lines of VHDL code) causes a segmentation fault in QuestaSim.
Regards
Patrick
# Attempting stack trace sig 11
# Signal caught: signo [11]
# vsim_stacktrace.vstf written
# Current time Thu Sep 03 23:39:47 2015
# QuestaSim Stack Trace
# Program = vsim
# Id = "10.2c"
# Version = "2013.07"
# Date = "Jul 19 2013"
# Platform = win64
# End of Stack Trace
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading poc.my_config(body)
# Loading poc.utils(body)
# Loading poc.arith(body)
# Loading ieee.math_real(body)
# Loading poc.my_project(body)
# Loading poc.config(body)
** Fatal: (SIGSEGV) Bad pointer access. Closing vsimk.
** Fatal: vsimk is exiting with code 211.
(Exit codes are defined in the QuestaSim messages appendix
of the QuestaSim User's Manual.)
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How to create decal with odd shaped Pad and PCB cutout
Hi, I'm trying to create a decal for a component which has some odd shaped pads pictured below:
The inner outline is a hole. Any ideas how I can create this L shaped through hole? I understand how to create a copper pour and associate it with the PAD, but what about the L shaped hole, which needs to be indicated plated through?
Also, another section of the decal requires a board cut out as follows:
Any ideas on how to place a board cutout within the decal? Is a line drawing on the Drill Drawing layer sufficient to indicate a cutout?
Thanks in advance for the help!
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Error while generating allegro netlist
Hi,
While generating allegro netlist I am having below error
Error 6052: design com $57I1440 Duplicate name: F30
Error 6052: design com $57I1459 Duplicate name: F30
Error 6052: design com $57I1421 Duplicate name: F30
Error 6052: design com $57I1440 Duplicate name: F30
Can anyone help me on this ?
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How to define clearance for a net or a part
I need to define 7mil trace to pad clearance for all pads on a connector. The master is 10mil and it says it is read only from Expedition.
I see that there is no place to give a net or part clearance rules. Please help.
The CES is very confusing.
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Sourcery CodeBench - How can I add an additional Base Board with the software package that I have for AT91SAM9G25 Atmel Board/CPU
Hi,
I am just a beginner for Mentor Sourcery CodeBench and currently working on the evaluation copy to understand its features.
I would appreciate it very much if you could tell me how to add an additional "Base Board" by using the software package (sam9g25_softpack_1.0_for_CodeSourcery_2010q1 zip ) released by Atmel for AT91SAM9G25 Atmel CPU/Board.
Basically, what I need is to add Atmel AT91SAMG25-EK into the Sourcery CodeBench and select it from the Baseboard list as shown below.
Thank you very much for your support in advance...
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The State of the Mentor EE7.x Symbol and PCB Footprint Library Creation tools.
One of the Aberdeen reports said that (I'm paraphrasing here) "One of the core requirements to having a robust E-CAD system is having a good PCB library". The Mentor library tools make this difficult. Here are some examples:
- Mentor now has 3 symbol editors, the New Symbol Editor, the FPGA Symbol Editor and IO Designer. Now our librarians need to learn at least 3 different tools to build symbols depending on the type of part. None of these tools can easily create a large pin count ICs (other than FPGAs and ASICs) that can handle fractures and keep track of the pins between the fractures. None of these tools can mine the pin data from a vendor's component specification PDF file.
- There are 2 cell editors, the Cell Editor (which is basically Expedition) and the LP Wizard. Again the librarians have to learn 2 different tools to build cells depending on the type of cell being created. Anything built using the LP Wizard must be brought into the Cell Editor to be finished. More tools for the librarians to use.
- One of the keys to using CES is having a good model library. Mentor has no tools in this area that make it easy for users to add IBIS models to the library to support CES.
- There are also no tools to add SystemVision models to our parts in our library.
All these different tools make it much more difficult for librarians to create library parts. In our environment we add on average 300 parts a month to our library. Our librarians need one robust tool to create library parts, both in the netlist flow and the Expedition flow. In my opinion, because Mentor has no one group in SDD responsible for librarian tools, all we have now is a bunch of point tools that address certain types of parts. Mentor needs to get organized, quit the infighting between the different factions and quickly come up with a strategy to address this issue.
Do any other companies have this problem?
Thanks for listening,
Tony
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Fractured schematic part
Hello All,
I am new to Mentor Graphics CAD Software and I am trying to learn it on the online demand class. I am having problem placing a fracture component into the schematic. Parts looks correct, however, when I go to place it using DxDatabook I can only the first of the fracture part. Can someone help me out?
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WHAT PC SPEC FOR THE 3D VX1.2?
DOES ANYBODY HAVE A SUGGESTION ABOUT A GOOD SPEC PC FOR THE 3D CAPABILITIES OF PADS STANDARD+ ?
REGARDS
jOHN tODD
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Migration from Netlist based design to Central library based
Migration from Netlist based design to Central library based is proving to be impossible , mostly because of the packager related errors.
Starting from square one, dancing around the issues would be easy BUT!!!!
I have a very large database of symbols , in both dxdesigner and pads that is linked by a dxdatabook tables of more that 3000 parts.
I used the Central Library Migrator to create the central library, there were a lot of warning and some errors. I assumed I would be able to work around them.
This is where my problems start,
I took a completed and in production design created in netlist flow and converted it to Integrated.
It is just one giant bucket of errors. though all the data needed is there and good.
The biggest problems is the "PART" area,its associations and the need foboth symbol and decal to be correctly associated.
many parts are not associated to symbols. simply because the "GATE" and "CAE DECAL" are missing, wrong or incomplete in pads.
Most of out part database does not have or need this info , and the schematic goes forward and backwards fine without it in netlist flow.
Because the Packager insists on validating this info, and in a certain set of cases, it is impossible to set it correctly.
problem 1: some of our symbols , use ".1,.2,.3,.4" ' still very selectable in dx designer part and still works in integrated mode for part selection.
,cannot be import into central library because there are no extension , schematic entry still works, packager fails and cannot be made to work, no extensions on symbol names importable, so only the ".1 "version will ever exist in the central part library.
problem 2: I have some duplicate and identical symbols {not on purpose} in two or more partitions ,
schematic entry still works, packager fails and cannot be made to work. no partition info in part name so it cannot set symbol from correct partition. works if lucky , else never works ,
problem3: MUST have a "cae decal" defined, does not do anything I can see that is useful, but cannot be possibly be set right if problem 1 or 2 applies .
problem4: MUST have a Gate and correct pin names, does not do anything I can see that is useful, can be a massive manual editing job on large I.C. and cannot be set right if problem 1 or 2 applies .
Most of the migration process left symbols and decal association unset because of the previous problems. we are talking like way more than 1/2 of my database is not usable .....
Most of the problems are based on rules and input that applies to pads schematic entry and has no bearing on dxdesigner.
as a matter of fact my base Pads library has NO schematic decals at all, but all of the packager test against this hierarchy which is not compatible to dxdesigner in many cases.
Remember this is a design that was fully forward and back annotated and built using netlist flow but I cannot get past packager forward without a lot of errors ,
all the errors are rooted in the packager verifying that PADS schematic symbols as correct for the part, and schematic symbols are not really relevant to layout, but it keeps me from going to layout.
simple question , can I turn off the packagers check of the schematic symbol to part db integrity????
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how to get demonstration enable code for hyperlynx ?
Hi everyone
i am new bie for hyperlynx. i need to enable the demonstration enable code for hyperlynx how to enable ?? for whom i need to contact ??please reply anyone
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plane shape refresh 방법 문의
Component의 pin을 Buried 하고자 합니다.
아래와 같이 Script 실행 하면 Pin의 TieLegType은 변경 되지만 Plane shape은 변화가 없고 이전 상태로 보입니다.
하여 plane shape을 refresh 하고 싶은데 어떻게 하면 되는지요?
Set Compscoll = pcbDoc.Components
For Each ocomp In Compscoll
Set pinscoll = ocomp.pins
For Each opin In pinscoll
opin.TieLegType = 4 'epcbTieLegBuried
Next
Next
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Unable to adjust number of section in borders (VX1.1)
Hello everyone,
I am attempting to adjust the B size border from the default 2x4 sections to be 5x10 sections. I have been completely unsuccessful and could use some guidance. As it is the borders in PADS VX 1.1 seem to be scaled very large compared to the actual paper size, the B size block measures 2" x 6" when I print it.
Thanks
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Kernalbase.ddl
Hi There,
I have installed mentor Expedition and it crashes as soon as I open it with fault module KERNELBASE.dll
I googled a lot and it seems like it is such a nasty problem and I have already done sfc /scannow and came up with 100% verification
any ideas?
Cheers,
-MR
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Error during Auto-routing wires using PRO-E.
Hi, i am new to vesys, please help me out in solving this error, i faced issue while auto routing the wires in pro_e.
Steps followed for exporting and importing from vesys 2.0 to PRO-E
1. Created wiring diagram , exported it as .nwf file.
2. Imported in to PRO-E, as neutral file.
3. Created the network path between two connectors in PRO-E.
4. Gave reference desiginator and Entry port correctly.
When tried to do the auto routing, the error came as , "already the wires has been routed" also i have taken the screen shot of the error please find the attachment.
Thanks
Sharath.
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